Sergiyenko A., Klimenko I., Sergiyenko P.

 An approach to the reconfigurable computer design based on FPGAs is proposed. It is based on mapping the synchronous dataflow graphs into the many-core processor system in which the reconfiguration means the dataflow switshing. A soft core of the 16-bit RISC microprocessor is designed for this system, which has small hardware volume and configurable instruction set.

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