Dolgolenko A., Yatsun V.
This article describes addition/subtraction device operating on floating point numbers designed for cores of superscalar microprocessors and specialized hardware built using FPGA. The adder is designed as a set of combinational circuits without memory elements and without microprogram management. No additional actions are required for the adder to be reconfigured for processing operands of a required format but setting the required format into its control inputs.
